Research
RTL simulation stage

MiNTs-CPU

An in-order RV64IMAC CPU designed in SystemVerilog. Starting from the CPU design course at cpu.kanataso.net, we have extended it with Linux boot, lockstep verification against a reference model, and improvements guided by performance counters.

View the code on GitHub
CPU CORE / RV64IMAC / IN-ORDER 5-STAGEIFFETCHBPREDITLBI-CACHEIDDECODEREGFILEEXALUBRANCHMUL/DIVFORWARDMEMDTLBPMPD-CACHESTORE BUFWBWRITEBACKRETIREMMU / PROTECTIONSV39 PTWPMP CHECKVERIFICATION / MEASUREMENTWHISPER LOCKPERF COUNTI/D ARBITER / MMIO DECODEBOOT ROMRAMUARTPLICACLINTDEBUG
FIG.1 Simplified structure of MiNTs-CPU. Operation has been confirmed in RTL simulation on Verilator.
61,610,275
Instructions matched in lockstep comparison with Whisper
54 / 54
rv64ui tests passed
CPI 2.393
Measured over 100M cycles of Linux boot, down from 2.529

FIG.2 Branch-heavy loop

The cycle gap with Rocket Chip has almost closed

Total cycles of MiNTs-CPU minus total cycles of Rocket Chip, on the 1x loop.

  • Before improvements

    +19,968

  • Fetch-side BTB added

    +9,970

  • Fetch / issue bypass added

    −31
View all values in a table
Cycles1x2x4x
Rocket Chip70,04565,04262,545
MiNTs-CPU: Before improvements90,01375,02567,537
MiNTs-CPU: Fetch-side BTB added80,01570,02765,039
MiNTs-CPU: Fetch / issue bypass added70,01465,02662,538

Comparison on a branch-heavy loop using common RV64 integer assembly. This does not mean overall CPU performance is equivalent to Rocket Chip. Values come from simulation, not from silicon or FPGA.

Read the measurement details on Qiita (in Japanese)

Implementation

Current implementation

ISA
RV64IMAC
Pipeline
In-order, 5 stages
Privilege modes
M / S / U
Virtual memory
Sv39, shared PTW, ITLB, DTLB
Memory protection
8-entry PMP (checks instruction, data, and PTW physical accesses)
Caches
4 KiB I-cache, 16 KiB D-cache (write-through), 8-entry store buffer
Branch prediction
2-bit PHT, fetch-side BTB, JALR BTB, RAS
Interrupts and peripherals
ACLINT, PLIC-compatible controller, NS16550A-compatible UART
Boot
OpenSBI v1.3.1 → Linux 6.12 → BusyBox
Verification
riscv-tests, custom C tests, Linux boot, Whisper lockstep

Limitations

Not yet supported

  • F / D floating point
  • Zb* bit manipulation
  • SMP / cache coherence
  • Stable write-back D-cache
  • Full RVA23 compliance
  • Timing closure on FPGA

Joint research and technical collaboration

Collaborate with us

MiNTs-CPU is at the research stage and is not offered as a product or service.

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