Implementation
We have implemented a five-stage pipeline, branch prediction, caches, Sv39 virtual memory, and physical memory protection, and have confirmed that the design boots Linux.
- RV64IMAC
- PHT / BTB / RAS
- I / D-cache
- Sv39
- PMP
Research
Inside the CPU.
We build on RISC-V, an open instruction set architecture with room to grow. Through design, implementation, measurement, and verification, we investigate processor constraints and ways to address them.
Focus
Research focus
We advance our research in processor microarchitecture through iterative implementation, verification, and performance analysis.
Verification
In addition to running riscv-tests, we use lockstep verification to compare instruction execution against the Whisper reference model. We have also verified Linux boot and automated BusyBox tests.
- riscv-tests
- Whisper
- Lockstep
- Verilator
- BusyBox autotest
Performance Analysis
We analyze where cycles go using performance counters and compare against public cores using common assembly. We also state clearly what the results show and where they apply.
- Performance counters
- CPI
- Microbenchmark
- Rocket Chip
Outputs
Published work
MiNTs-CPUAn RV64IMAC CPU that boots Linux. See its specifications, verification, and measurement results.View detailsTechnical articles (in Japanese)
- 2026.08Comparing our CPU with Rocket Chip and improving its branch predictor
- 2026.07Understanding PMP through a custom RISC-V CPU: physical memory protection for running OpenSBI and Linux
- 2026.07What is SETSSIP in RISC-V? Understanding the "doorbell" for inter-hart notification
- 2026.02A summary of the Sv32 specification for translating a VA through a PTE to a PA
- 2026.02Notes on understanding MMIO (memory-mapped I/O)
- 2025.12Lessons from converting Veryl to SystemVerilog
Next
What's next
FPGA implementation
Synthesizing the current stable configuration and checking its timing.
Memory system
Evaluating write-back mode and improving the store buffer.
Benchmarks
Adding CoreMark and Embench to widen the scope of comparison.
AI and security
We are interested in computing platforms for AI workloads and in hardware-based memory safety.
Joint research and technical collaboration
Collaborate with us
The work described here is at the research stage and is not offered as a product or service.